Experience
2026 – Present
Independent Advisor & Consultant – Silicon & AI-Native Chip Design
Advising AI chip startups, EDA companies, and hardware-focused investors on AI-native chip design methodology, silicon architecture, ultra-low-power design, and EDA strategy. Active engagements include:
Author & Publisher – Above the RTL
Practitioner-oriented publication on AI-driven chip design methodology. Recent work includes multi-model CDC analysis benchmarking across Claude, Gemini, ChatGPT, Qwen, and Gemma; metastability physics and fan-out coherence analysis; the five-phase AI-native design pipeline framework (spec formalization → contract extraction → implementation generation → verification synthesis → continuous compliance); and a stateful MCP server exposing Verific-based RTL analysis to AI coding agents for multi-turn RTL exploration, lint, CDC queries, and contract extraction.
Chief Engineer, Wearables Silicon
Appointed Chief Engineer with company-wide accountability for technology strategy, design methodology, and power integrity across the Wearables Silicon portfolio. Led the AI-native methodology transformation of a 450–500-person design organization spanning design, verification, DFT, CAD, and PD, while serving as Chief Engineer on Meta’s first dedicated AI accelerator chip.
2020 – 2022
Director of Silicon – SoC Design & Architecture
Promoted to Director to build and lead Meta’s internal SoC execution function. Directly responsible for architecture, design, verification, and DFT across the Wearables SoC portfolio, with all chip architects reporting directly.
2018 – 2020
Senior Manager / Senior Chip Lead
Joined as one of the early individual chip leads when Meta established its in-house silicon function, reporting directly into the VPs who built the organization from scratch. Promoted to Senior Manager as the team scaled, overseeing multiple SoC programs.
2011 – 2018
Associate VP of Engineering – IoT Turnkey Projects
Led all IoT turnkey chip development from architecture through tape-out and silicon validation, with full accountability for program wins, delivery, and client relationships. Served as the technical face of Synapse to founders, CEOs, and senior VPs at Intel, AMD, GlobalFoundries, Megachips, and Verizon.
2011 – 2013
Director of Engineering – Europe
Established and managed Synapse’s European engineering presence, building the regional team and developing relationships with key European semiconductor customers.
2004 – 2011
ASIC Design Manager – Communications Infrastructure Division
Led ST’s dedicated ASIC design team for Cisco with full-stack ownership across design, DV, physical design, DFT, test program bring-up and debug, and qualification testing. Served simultaneously as ST’s DFT architect and as the joint STM–Cisco DFT representative.
2000 – 2004
Project Lead / Senior Designer – Wireline Division
Progressed from senior designer to project lead on wireline ASIC programs within ST’s Communications Infrastructure group.
Results
Drove the silicon strategy behind Meta’s Orion AR glasses
As Chief Engineer of Wearables Silicon at Meta Reality Labs, Marco set technology direction for the chipset powering Meta’s Orion AR glasses, unveiled at Meta Connect 2024. The program required breakthrough decisions in ultra-low-power architecture, on-device AI compute, and design methodology to make the form factor possible.
Led an AI-native methodology transformation across a 500-person silicon organization
At Meta Reality Labs, Marco led the AI-native methodology transformation of a 500-person silicon design organization, embedding AI-driven practices across architecture, verification, and tape-out. The shift moved a large legacy organization to AI-native design at production scale.
Delivered a $31M turnkey LTE IoT modem program at Synapse Design
Owned and delivered a $31M LTE IoT modem turnkey program by engaging both a Verizon-backed startup and Verizon directly, a 3-chip set designed for 2–3 year battery life on a coin cell, which achieved Verizon Safe for Network certification on the A0 silicon.
Expertise
AI-Native Chip Design Methodology
Spec-First Design by Contract
LLM Evaluation for Hardware Verification
Formal Verification
CDC/RDC Analysis
MCP Tooling for EDA Integration
SoC Architecture & Delivery
AI Accelerator Design
AR/VR Silicon
Ultra-Low-Power Design
FD-SOI & Sub-Threshold
Adaptive Voltage Scaling
Technology Node Selection & Roadmap
EDA Vendor Strategy
DFT & BIST
Long-Lifecycle Qualification
IoT & Wearable Silicon
Turnkey ASIC Delivery
Patents & IP Development
Cross-Functional Engineering Leadership
Global Team Management
Client-Facing Technical Leadership
AI Transformation of Hardware
Organizations
Education
Master of Science in Electronic Engineering
Laurea, 5-year Program
University of Pavia, Italy
Meet Marco
Testimonials
“I am sad you are leaving us, you were the one fighting for us and giving us visibility.”
Senior Designer, STMicroelectronics
Q & A
Why did you choose your profession?
I have had an interest in technology since I was a kid, to the point that when I was in 5th grade it was already obvious I’d end up in engineering school one day.
I chose what I do now because I love to work on complex systems, understand and analyze what consequences each decision we make has at the overall project level, and see a whole system come to life, often from a PowerPoint or Word document.
What is your greatest accomplishment?
I think the Orion chipset and the LTE+GPS modem are the technical accomplishments.
From the team level, I have created the SoC execution team at Meta by myself, and I have mentored several of them to very senior positions, including one whom I promoted from senior engineer to technical director (IC6 to IC8 in Meta), and another from senior engineer to now a senior director (he now reports to the VP), as well as creating the very first senior Verification manager in the organization.
What tools do you use?
Lately I have mostly used the AI tools, especially Claude, and from the EDA point of view I have used or understand the entire design to physical flow from Synopsys, Cadence and, in smaller part, Mentor (Siemens).
What advice would you give to someone just starting out in your profession?
Be the curious person, the one who understands why and not just what we do, how every decision impacts the rest of the system. Be the one who asks and embraces the new stuff.
The method I use to judge how well a new hire is integrating and progressing is to gage what questions they ask.
It’s the progression of the depth and insight into those questions that tells me a lot more than asking questions myself.